The present invention relates generally to semiconductor device processing and more particularly to apparatus and methods for determining or characterizing floating body effects such as hysteretic propagation delays in SOI devices.
A continuing trend in the semiconductor manufacturing industry is toward smaller and faster transistor devices, which consume less power. Toward that end, device scaling is a continuous design goal, wherein device features sizes and spaces are reduced. However, performance limits are reached in technologies where scaled transistors and other electrical devices are formed directly in a wafer substrate, such as silicon. These are sometimes referred to as bulk devices. To surpass the performance limitations of bulk devices, recent scaling efforts have included the use of silicon over oxide (SOI) wafers, in which a silicon layer overlies an insulator layer above a silicon substrate. SOI wafers may be fabricated according to known SOI wafer manufacturing techniques, such as SIMOX, bond-and-etch-back and smart-cut technology.
In SOI wafers, the active semiconductor regions of the wafer arc formed in the silicon on top of the oxide insulator, whereby these active regions are electrically isolated from one another. This technique achieves certain design advantages, such as a significant reduction in parasitic capacitances that exist in non-SOI (bulk) devices, as well as enhanced resistance to radiation damage. Partially depleted SOI devices are produced using one type of SO process in which the transistors are formed in a deposited semiconductor layer which is thick enough that the channel region will not be fully depleted through its full thickness when the device is in operation. The transistor design and operation in partially depleted SOI processes are similar to that of bulk CMOS devices.
Although SOI designs provide certain advantages over bulk designs, SOI devices suffer from certain effects related to the isolation of the active devices from the substrate material underlying the oxide layer, which are sometimes referred to as floating-substrate or floating body effects. In bulk transistors, the transistor body may be electrically connected through the substrate. In this case, the transistor body is at a relatively fixed potential, and consequently, the transistor threshold voltage is stable relative to the drain-to-source voltage. In many SOI transistors however, the body (e.g., the undepleted silicon under the gate) is electrically floating with respect to the substrate because of the intervening oxide insulator layer. Thus, when sufficient drain-to-body bias is applied to the transistor, impact ionization can generate electron-hole pairs near the drain. These electron-hole pairs cause a voltage differential to build up between the body node and the source of the transistor because majority carriers travel to the body while the minority carriers travel to the drain. The resulting voltage differential lowers the effective threshold voltage, thereby increasing the drain current.
The isolated body creates capacitive coupling between the body and the gate, between the body and the source, and between the body and the drain, in addition to diode couplings between the body and the source and between the body and the drain. These effects bias the body, creating a variation in the transistor threshold voltage during switching which is dependent upon the current and past states of the transistor. During switching, these effects bias the body through two mechanisms; capacitive coupling between the body and the gate, source, and drain, as well as charging and discharging between the body and the source and drain through diode coupling. This history dependent operation, sometimes referred to as hysteretic behavior, results from potentially large uncertainties in the floating body potential and, thus, uncertainties in the threshold voltage of devices due to unknown switching history.
These floating body effects can contribute to undesirable performance shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics. In order to address these SOI floating body issues, some designs provide for electrical connection of the body or the source of an SOI transistor to the substrate. Transistors formed in this manner in an SOI wafer are sometimes referred to as tied body transistors. Although this technique serves to prevent body charging by creating a direct contact to the substrate, implementation of this approach complicates the device manufacturing process and also increases area overhead because tied body devices consume a larger area than floating body devices. Thus, most SOI designs must take these floating body effects into account.
Because these and other floating body issues affect end-product device performance, monitoring the hysteretic behavior of SOI devices is needed to refine and monitor the SOI manufacturing process. Thus, it is desirable to measure floating body effects in wafers at various points in a manufacturing process flow. One measure of the veracity of an SOI process is the propagation delays in switching a floating body transistor from one state to another. The threshold voltage of such floating body devices is dependent upon the body potential. The body potential, in turn, is dependent upon the current and past states of the transistor (e.g., the voltages at the various terminals of the device). Thus, the propagation delays are often measured at various voltages with switching signals of varying amounts of preconditioning, to obtain a curve of average propagation delay vs. time.
Typically, these measurements are obtained manually on a test bench, using oscilloscopes and high frequency probes to monitor floating body transistor switching delays under various conditions. Pulse generators are connected to the inputs of inverters or other floating body devices, which are formed of floating body MOS transistors, and the device outputs are monitored using the oscilloscope. Such testing is time consuming, and ill fitted for testing every wafer in a high throughput production setting. Thus, there is a need for improved apparatus and methods for measuring hysteretic propagation delay in SOI devices, which are amenable to automation using readily available, inexpensive test equipment.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to apparatus and methodologies which may be employed to facilitate automated wafer testing to characterize hysteretic propagation delay and other floating body effects in SOI devices.
According to one aspect of the invention, test apparatus is provided, which comprises a floating body chain including a plurality of series connected floating body devices, such as inverters or NAND gates fabricated in a silicon over insulator (SOI) wafer and a reference delay chain comprising reference delay elements, such as tied body devices, connected in series in the wafer. The floating body comprises MOS transistors fabricated in the SO wafer. The reference delay elements may be some devices whose delay properties are switching-history independent, such as tied body inverters fashioned from MOS transistors having body regions or source regions electrically tied to the substrate. Storage elements such as edge-triggered registers or level-sensitive latches are formed in the wafer and coupled with the reference delay elements and with one or more of the floating body devices, where the storage elements operate to store reference delay chain data from the reference delay elements according to one or more signals from the floating body chain.
The storage elements may be divided into groups associated with odd and even reference delay elements, wherein the first group stores first reference delay data values from the odd numbered reference delay elements according to a first signal from the floating body chain and the second group stores second reference delay data from the even numbered reference delay elements according to a second signal. A pulse edge is applied to the floating body and reference delay chains, wherein the first control clock to the first group of the storage elements is provided when the pulse edge propagates through the floating body chain to a first floating body device, and the second clocking signal to the second group of the storage elements is provided when the pulse edge propagates through the floating body chain to a second (e.g., downstream) floating body device. A test system, such as a PC-based tester may then retrieve the first and second stored reference data, such as through a data interface in the wafer, and determine a first value representing a number of reference delay elements in the reference delay chain to which the pulse edge has propagated, as well as a second value representing a number of reference delay elements to which the pulse edge has propagated. A floating body delay value may then be determined according to the first and second values.
If the reference delay elements are implemented using tied body devices, prior to or following the provision of the pulse edge, and the tied body data loading, an odd number of the tied body devices may be selectively connected in a loop to operate as a ring oscillator for measuring a reference propagation delay value for use in evaluating the stored data In one example, a frequency divider is provided, which receives an output from one of the tied body devices in the tied body chain ring oscillator, along with a buffer receiving a divided count of transitions on the output of the tied body device from the frequency divider. This allows measurement of a tied body device propagation delay value. The loop is then decoupled, wherein the test pulse edge may then be applied to the tied body and floating body chains. The floating body delay value may then be determined according to the first and second values and according to the tied body device propagation delay value.
Another aspect of the invention provides test systems for characterizing floating body delay effects in an SOI wafer. The system comprises a floating body chain and a tied body chain, as well as a plurality of latches coupled with the tied body chain and with the floating body chain, wherein the latches are adapted to latch tied body chain data according to at least one of the floating body devices. The system further provides a tester comprising a pulse generator coupleable to the floating body and tied body chains so as to provide a pulse edge to first devices thereof. A processor is provided, which is coupleable to the latches to receive latched tied body chain data therefrom, and a power source is provided to power the devices in the wafer. The processor may control the pulse generator to selectively provide one or more pulse edges to the floating body and tied body chains and further determines at least one floating body delay value according to the tied body chain data from the latches.
Yet another aspect of the invention provides methods for fabricating an SOI wafer, comprising providing a plurality of series connected floating body devices in the wafer to form a floating body chain, providing a plurality of series connected tied body devices in the wafer to form a tied body chain, and providing a plurality of latches in the S wafer, where the latches are individually coupled with the tied body devices and with one or more of the floating body devices. The latches latch tied body chain data from the tied body devices according to the floating body device or devices in the floating body chain. The method further comprises providing one or more pulse input pads in the wafer, which are coupled with a first one of the floating body devices and with a first one of the tied body devices, as well as providing an interface coupled with the latches in the wafer to provide external access to the tied body chain data.
According to still another aspect of the invention, methods are provided for measuring or characterizing hysteretic propagation delay or other floating body delay effects in SOI devices. The methods comprise providing a pulse edge to a floating body and a tied body chain in an SOI wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects, such as by determining one or more floating body delay values, according to latched tied body chain data. The tied body chain data storing may comprise storing first tied body chain data according to a first floating body device and storing second tied body chain data according to a second floating body device after storing the first tied body chain data.
In one implementation, first data states are latched from the tied body devices when the pulse edge propagates through the floating body chain to the first floating body device, and second data states are latched when the pulse edge propagates to the second floating body device, wherein the first states may represent odd numbered tied body device states and the second states represent even numbered tied body device states. First and second values may be determined from the latched data, which represent the number of tied body devices to which the pulse edge has propagated in the chain at the points in time where the pulse edge reaches the first and second floating body devices. These values are then used to determine a floating body delay value.
The method may further comprise coupling first and last tied body devices in the tied body chain to form a tied body chain ring oscillator, measuring a tied body device propagation delay value using the tied body chain ring oscillator, and decoupling the first and last tied body devices from one another in the tied body chain. In this instance, the floating body delay value may be determined according to the first and second values and according to the tied body device propagation delay value. Alternatively, or in combination, the method may also comprise providing one or more preconditioning pulses to the floating body chain and to the tied body chain before providing the pulse edge, so as to provide an indication of the floating body propagation delay in the presence of hysteretic preconditioning.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.